Details

<p>Introduction.- Process Variation Challenges and Solutions Approaches.- High-Linearity Transconductance Amplifiers with Digital Correction Capability.- Multi-Bit Quantizer Design for Continuous-Time Sigma-Delta Modulators with Reduced Device Matching Requirements.- An On-Chip Temperature Sensor for the Measurement of RF Power Dissipation and Thermal Gradients.- Mismatch Reduction for Transitiors in High-Frequency Differential Analog Signal Paths.- Summary and Conclusions.</p>

<p>This book describes several techniques to address variation-related design challenges for analog blocks in mixed-signal systems-on-chip. The methods presented are results from recent research works involving receiver front-end circuits, baseband filter linearization, and data conversion. These circuit-level techniques are described, with their relationships to emerging system-level calibration approaches, to tune the performances of analog circuits with digital assistance or control. Coverage also includes a strategy to utilize on-chip temperature sensors to measure the signal power and linearity characteristics of analog/RF circuits, as demonstrated by test chip measurements.    </p><ul><li>Describes a variety of variation-tolerant analog circuit design examples, including from RF front-ends, high-performance ADCs and baseband filters;</li><li>Includes built-in testing techniques, linked to current industrial trends;</li><li>Balances digitally-assisted performance tuning with analog performance tuning and mismatch reduction approaches;</li><li>Describes theoretical concepts as well as experimental results for test chips designed with variation-aware techniques.</li></ul><p>

Describes a variety of variation-tolerant analog circuit design examples, including from RF front-ends, high-performance ADCs and baseband filters Includes built-in testing techniques, linked to current industrial trends Balances digitally-assisted performance tuning with analog performance tuning and mismatch reduction approaches Describes theoretical concepts as well as experimental results for test chips designed with variation-aware techniques Includes supplementary material: sn.pub/extras