Details

Introduction to System-on-Chip Design using Network-on-Chip.- Network-on-Chip Security Challenges due to Supply Chain.- Characterizing and Optimizing Performance in NoC Architectures.- Characterizing and Optimizing Energy in NoC Architectures.- Modeling NoC in Architectural Simulators.- Eavesdropping Attacks.- Data Integrity Attacks.- Denial-of-Service Attacks.- Side-Channel Attacks.- Emerging Security Vulnerabilities in NoC-based SoCs.- Lightweight Encryption and authentication in NoC-based SoCs.- Trust-aware Routing in NoC-based SoCs.- Route and Data Randomization in NoC-based SoCs.- Mitigating Side-Channel Attacks in NoC-based SoCs.- Real-time Detection and Localization of DoS attacks.- Digital Watermarking for Detecting Malicious IP Cores.- Authorization for NoC Resource Accesses.- Formal Verification of NoC Security Properties.- NoC Trust Verification using Security Assertions.- Securing Optical/Photonic NoC.- Securing Wireless NoC.- Securing 2.5 and 3D NoC.- Future of TrustworthyOn-Chip Communication.- Conclusions and Future Directions.&nbsp;<p></p><p></p>

<p></p><p><b>Prabhat Mishra</b> is a Professor in the Department of Computer and Information Science and Engineering and a UF Research Foundation Professor at the University of Florida. Prior to joining University of Florida, he spent several years in various companies including Intel, Motorola, Sasken, Synopsys and Texas Instruments. He received his Ph.D. in Computer Science from the University of California at Irvine. His research interests include embedded and cyber-physical systems, hardware security and trust, computer architecture, energy-aware computing, formal verification, system-on-chip validation, machine learning, and quantum computing. He has published 8 books, 35 book chapters, and more than 200 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award from the National Science Foundation, IBM Faculty Award, ten best paper awards and nominations, and EDAA Outstanding DissertationAward from the European Design Automation Association. He has served as an Associate Editor of IEEE Transactions on VLSI Systems, ACM Transactions on Design Automation of Electronic Systems, IEEE Design & Test, and Springer Journal of Electronic Testing. He has served on the organizing and program committees of several leading international conferences. He is an IEEE Fellow and an ACM Distinguished Scientist. &nbsp;</p>

<p><b>Subodha Charles</b> is a faculty member in the Department of Electronic and Telecommunication Engineering at the University of Moratuwa, Sri Lanka. He received his Ph.D. in Computer Science from the University of Florida, USA, and his B.Sc. in Electronics and Telecommunication Engineering from the University of Moratuwa, Sri Lanka. His research interests include hardware security and trust, embedded systems, and computer architecture. He has published one book, nine book chapters, and more than ten research articles in premier international journals and conferences. He has gathered industry experience at Intel, USA and Zone24X7, Sri Lanka. Subodha co-founded a company in Sri Lanka operating in the energy sector in 2013 and is currently one of the country's market leaders. The company has invested in other areas such as healthcare and construction and is also exploring further expansion possibilities. He has volunteered at IEEE (Institute of Electrical and Electronics Engineers) since 2011 and has held several global leadership positions. He has successfully led many initiatives within IEEE to foster entrepreneurship, industry collaboration and membership growth. Several international awards within IEEE have recognized his efforts, including the best student volunteer in the Asia-Pacific region award in 2015.</p><br><p></p>

This book provides comprehensive coverage of Network-on-Chip (NoC) security vulnerabilities and state-of-the-art countermeasures, with contributions from System-on-Chip (SoC) designers, academic researchers and hardware security experts. Readers will gain a clear understanding of the existing security solutions for on-chip communication architectures and how they can be utilized effectively to design secure and trustworthy systems.<div><p></p><ul><li>Provides a comprehensive overview of NoC security vulnerabilities for diverse on-chip communication architectures, including bus, mesh, ring, star, and hybrid network topologies;</li><li>Describes state-of-the-art security solutions for defending against a wide spectrum of attacks, including malicious implants (e.g., hardware Trojans), eavesdropping, information leakage, spoofing, denial-of-service, and erroneous execution;</li><li>Covers a wide variety of NoC attacks and effective countermeasures for diverse communication technologies, including electrical, optical (photonic) and wireless NoCs; </li><li>Presents lightweight static (design-for-trust), as well as dynamic (runtime) security solutions; </li><li>Enables security validation using an effective combination of formal methods, assertion-based validation, side-channel analysis, and machine learning;</li><li>Discusses &nbsp;trade-offs between on-chip communication security and energy-efficient implementation in resource constrained embedded systems and &nbsp;IoT devices.</li></ul><p></p>









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onstrained embedded systems and IoT devices. Provides a comprehensive overview of NoC security vulnerabilities for diverse on-chip communication architectures, including bus, mesh, ring, star, and hybrid network topologies; Describes state-of-the-art security solutions for defending against a wide spectrum of attacks, including malicious implants (e.g., hardware Trojans), eavesdropping, information leakage, spoofing, denial-of-service, and erroneous execution; Covers a wide variety of NoC attacks and effective countermeasures for diverse communication technologies, including electrical, optical (photonic) and wireless NoCs; Presents lightweight static (design-for-trust), as well as dynamic (runtime) security solutions; Enables security validation using an effective combination of formal methods, assertion-based validation, side-channel analysis, and machine learning; Discusses trade-offs between on-chip communication security and energy-efficient implementation in resource c